Electrostatic discharge (ESD) occurs when large voltage pulses due to static electricity occur at the leads of an integrated circuit (IC). These large voltage pulses can cause the breakdown of insulating layers, short circuiting between conducting paths, or overheating or evaporation of metal or silicon pathways within the IC leading to the failure of the IC. Increases in IC density have reduced the width of IC traces and the gate dielectric thickness of active devices which have made ICs more susceptible to damage from ESD events.
During the processing and handling of individual packaged ICs, circuits connected to external pins, or external bumps in some IC packages, can be exposed to very high voltages. Peripheral circuits therefore use special electrostatic discharge (ESD) protection circuits coupled to external pins. However, ESD protection devices can cause signal loss at the inputs and outputs of the operating circuit. Some design techniques have been implemented to reduce this signal loss. Many of these designs use large ESD diodes. However, large diodes have large parasitic capacitances, which cause performance reductions. There is a tradeoff between parasitic capacitance and ESD robustness.